The present invention relates generally to memory devices and in particular the present invention relates to memory bank addressing.
Memory devices such as dynamic random access memories (DRAM) include memory cell arrays to store data. The memory array is typically arranged in addressable rows and columns. Often, the array is also arranged in numerous addressable banks. These banks can be physically separated on the memory die and have separate access circuitry. As such, row, column and bank addresses are used to read and write to the memory.
The number of memory array banks provided in a memory device can limit data access speed of the memory. That is, a memory device that has two banks allows the second bank to begin access operations while the first array is accessed. Likewise, additional array banks increase the likelihood that requested data is stored in different banks. Because repeated assesses to the same bank fail to take advantage of the parallel bank access functionality, an increased number of banks is advantageous.
Memory device manufactures attempt to make new generations of memory devices compatible with prior memory device generations. This compatibility allows one device to be manufactured without making the prior generation obsolete. If the new generation is not compatible, two or more generations are required to support current systems and future systems. Reverse compatible memory devices having a different number of array banks has proven difficult. For example, a new memory design with eight banks has different addressing and physical layout than a four-bank memory device. As such, both four and eight bank memory devices must be manufactured.
Memory manufactures have provided options that can change the capacity of a memory to reduce power consumption. For example, the memory array and addressing can be modified to reduce storage capacity. By reducing the memory size, portions of the array can be eliminated from refresh operations. While this option reduces power consumption, it does not provide a viable option to configure a memory without reducing the memory capacity.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device that can be configure with variable sized array banks.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises an array of memory cells arranged in a plurality of addressable banks, each bank comprises addressable rows and columns of memory cells, a mode register, and address circuitry coupled to the mode register to configure the addressable banks in response to a program state of the mode register.
In another embodiment, a dynamic random access memory comprises an array of X memory cells, a mode register, and address circuitry coupled to the mode register to configure the array in response to a program state of the mode register. The mode register defines a number of addressable banks of the array.
A synchronous dynamic random access memory (SDRAM) comprises an array of X memory cells, a mode register, a column address decoder, a row address decoder, and a bank address decoder. Address signal circuitry is coupled to a plurality of address signal input connections and routes a selected one of the plurality of address input connections to either the row or bank address decoder in response to data stored in the mode register.
A method of operating a memory device comprises programming a mode register of the memory device, and adjusting address circuitry of the memory device in response to the programmed mode register. The address circuitry configures a number of addressable banks of a memory cell array.